1. Field of the Invention
The present invention relates to a metal interconnect for a semiconductor device and a method of forming the metal interconnect for the semiconductor device. In particular, the present invention relates to a metal interconnect formed using insulating sidewalls formed from an insulating layer and a method for forming the same.
2. Description of Related Art
Typically, metal interconnects are formed from copper, tungsten, aluminum, or their alloys. The metal interconnect functions as a contact with devices, an interconnect between devices, and a connection between a chip and an external circuit. As semiconductor devices become more integrated, the contact size of the metal interconnect decreases and the aspect ratio in the metal interconnect layer increases. Furthermore, as the height of the capacitor increases, the degree of protrusion or sinking between cell regions and neighboring circuit regions also increases. Consequently, the lithography and etching processes necessary for forming the metal interconnect become increasingly more difficult.
FIGS. 1a–1c illustrate, in cross-sectional views, a conventional process for forming a metal interconnect in which a trench or a via hole is formed using a photoresist. A via hole 3 and a first interlayer dielectric layer 2 are formed on a lower metal interconnect layer 1. The dielectric layer 2 has a low dielectric constant. A metal layer 4 is deposited on the via hole 3 and the first interlayer dielectric 2, as shown in FIG. 1. The metal layer 4 is deposited by sputtering. The metal layer 4 is then planarized by Chemical Mechanical Polishing (“CMP”). A photoresist 5 is then spread and patterned on the deposited metal layer 4, as shown in FIG. 1b. A metal interconnect 6 is then formed by etching the exposed metal layer 4 not protected by the photoresist 5, as shown in FIG. 1c. A dry etch using plasma can be used to remove the exposed metal layer 4. The photoresist is then removed.
This conventional method for forming a metal interconnect requires a process of patterning with the photoresist to form a metal pattern or a via pattern. These methods present limitations in forming fine patterns because of the use of existing lithography alignments.
Others have attempted to form metal interconnects and gates without using photoresists. For example, Korean Patent No. 1995-0021029 discloses a method of forming a gate by forming a pattern using a thin upper insulating layer rather than a photoresist. The Korean Patent No. 1995-0021029 does not form the pattern using sidewalls.
Korean Patent No. 2000-0004334 discloses a method of forming a metal interconnect using a spacer layer rather than a photoresist. The method includes forming an HDP oxide on a substrate. A first nitride layer is deposited on the HDP oxide. A photoresist pattern is then formed on the first nitride layer. A trench is formed by selectively etching the first nitride layer and a portion of the HDP oxide. A second nitride layer is then formed on the first nitride layer and within the trench. The second nitride layer is etched to form a spacer layer, which exposes a portion of the HDP oxide. The exposed HDP oxide is then etched to expose a portion of the substrate. The spacer layer and the first nitride layer are removed to form a contact hole. The contact hole is then formed with metal to form a metal line. The relation between the hole and the metal line is unclear. Further, some problems may happen in designing a substrate, although the cross-sectional view of the process on the substrate does not reveal apparent problems.